A low-power asynchronous VLSI FIR filter

An asynchronous FIR filter, based on a Single Bit-Plane architecture with a data-dependent, dynamic-logic implementation, is presented. Its energy consumption and sample computation delay are shown to correlate approximately linearly with the total number of ones in its coeflcient-set. The proposed architecture has the property that coefficients in a Sign-Magnitude representation can be handled at negligible overhead which, for typical filter coefficient-sets, is shown to offer significant benefits to both energy consumption and throughput. Transistor level simulations show energy consumption to be lower than in previously reported designs

Alien Registration- Grass, Mary E. (Mars Hill, Aroostook County)

https://digitalmaine.com/alien_docs/33911/thumbnail.jp

Alien Registration- Grass, Eldridge E. (Mars Hill, Aroostook County)

https://digitalmaine.com/alien_docs/33910/thumbnail.jp

Alien Registration- Grass, Grace E. (Presque Isle, Aroostook County)

https://digitalmaine.com/alien_docs/33551/thumbnail.jp

GALS for Bursty Data Transfer based on Clock Coupling

In this paper we introduce a novel burst-mode GALS technique. The goal of this technique is improving the performance of the GALS approach for systems with predominantly bursty data transfer. This new technique has been used to implement a GALS-based version of a hardware accelerator of a 60 GHz OFDM baseband processor. The simulation results show a significant performance improvement in comparison with a classical implementation of GALS using pausible clocking. © 2009 Elsevier B.V. All rights reserved

GALS for Bursty Data Transfer based on Clock Coupling

In this paper we introduce a novel burst-mode GALS technique. The goal of this technique is improving the performance of the GALS approach for systems with predominantly bursty data transfer. This new technique has been used to implement a GALS-based version of a hardware accelerator of a 60 GHz OFDM baseband processor. The simulation results show a significant performance improvement in comparison with a classical implementation of GALS using pausible clocking. © 2009 Elsevier B.V. All rights reserved